regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
m5m5 v408bfp,tp,kv re v. 3.0e, feb. 12, 2001 4194304-bi t ( 524288-word by 8-bi t) c mos s tat ic ram mi t subishi lsis 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 i- v ersion -40 ~ +85c version, part name power s upply access time ( max.) 25 c stand-b y c urrent icc (pd) , vcc=3.0v 70 ns 2.7 ~ 3.6v 0.3a 1a t yp ical * 40 c 1 a 15 a 30 a 70 c 85 c 25 c 40 c 3 a 85 ns description ? single 2.7 ~ 3.6v power supply ? small stand-b y current: 0.3a (3v,t y p.) ? no clocks, no re f resh ? data retention suppl y v oltage=2.0v to 3.6v ? all inputs and outputs are ttl compatible. ? eas y memor y expansion b y s# ? common data i/o ? three-state outputs: or-tie capability ? oe# pre v ents data contention in the i/o bus ? process technolog y: 0.25m cmos features acti ve current icc1 30ma (10mhz) 5ma (1mhz) limit s (max.) 1 operating temperature the m5m5v408b is a f amil y o f low v oltage 4-mbit static rams organized as 524,288-words b y 8-bit, f abricated by mitsubishi's high-per f ormance 0.25m cmos technolog y. the m5m5v408b is suitable f or memor y applications where a simple inter f acing , batter y operating and battery (3.0v, t y p.*) *t y pical v alues are sampled, and are not 100% tested. ? package: m5m5v408bfp: 32 pin 525 mil sop m5m5v408btp: 32 pin 400mil tsop(ll) m5m5v408bkv: 32 pin 8mm x13.4mm stsop pin configuration (top vie w) a0 ~ a18 dq1 ~ dq8 s# ( s ) w# ( w ) oe# (oe) vcc gnd address input data input / output chip select input write control input output enable input power supply ground supply pin function outline 32p2m-a (sop) 32p3 y-h (tsop ii) a 9 oe# s# a 13 a 8 a 15 dq 6 dq 5 dq 4 dq 8 dq 7 a 11 w# v cc a 10 gnd d q 3 d q 2 d q 1 a 12 a 14 a 16 a 18 a 6 a 2 a 3 a 5 a 1 a 0 a 7 a 4 a 17 a 11 a 9 a 8 a 13 a 18 a 15 vcc a 17 a 16 a 14 a 12 a 7 a 6 a 5 a 4 w# oe# a 10 s# dq8 dq7 dq6 dq5 dq4 gnd dq3 dq2 dq1 a 0 a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 outline 32p3k-b (stsop) m5m5v408bkv m5m5v408b## -70h m5m5v408b## -85h m5m5v408b##-70hi m5m5v408b##-85hi 2.7 ~ 3.6v (## stands for "fp", "tp" or "kv") s tandard 0 ~ 70 c 0.3a 1a 1 a 15 a 3 a - 85 ns 70 ns
m5m5 v408bfp,tp,kv re v. 3.0e, feb. 12, 2001 4194304-bi t ( 524288-word by 8-bi t) c mos s tat ic ram mi t subishi lsis function table block diagram 2 mode dq icc s# w# oe# write read h l l l l x l h h h x x non selection high-impedance high-impedance acti ve standby read a 4 a 5 a 6 a 7 a 12 a 14 a 16 a 17 a 18 a 11 a 9 a 8 12 a 0 11 a 1 10 a 2 9 a 3 a 13 25 26 27 28 8 7 6 5 4 3 2 30 1 a 15 31 a 10 23 dq 1 dq 2 dq 3 dq 4 v cc (3v) gnd (0v) w# oe# dq 5 dq 6 dq 7 dq 8 s# 24 13 14 15 17 32 22 18 19 20 21 29 16 data input (d) acti ve acti ve memor y array 524288 words x 8 bits clock g enerator function the m5m5408bfp,tp,kv is organized as 524,288-words b y 8-bit. these de v ices operate on a single +2.7~3.6v power suppl y, and are directl y ttl compatible to both input and output. its f ull y static circuit needs no clocks and no re f resh, and makes it use f ul. a write operation is executed during the s# low and w# low o v erlap time. the address(a0~a18) must be set up be f ore the write c yc le a read operation is executed b y s etting w# at a high le v el and oe# at a low le v el while s# are in an acti ve when setting s# at a high le v el, the chips are in a non- selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high- impedance state, allowing or-tie with other chips. setting the oe# at a high le v el,the output stage is in a high- impedance state, and the data bus contention problem in the write c yc le is eliminated. the power suppl y c urrent is reduced as low as 0.3 a(25 c, t y pical), and the memor y data can be held at +2v power suppl y , enabling batter y back-up operation during power f ailure or power-down operation in the non- data output (q) 20 19 18 17 1 2 3 4 16 15 14 13 12 11 10 9 6 7 31 32 21 22 23 25 8 30 26 27 28 29 5 24 m 5m5v408bkv m 5m5v408bfp/tp m 5m5v408bkv m 5m5v408bfp/tp note: "h" and "l" in this table mean vih and vil, respecti v el y . " x " in this table should be "h" or "l".
m5m5 v408bfp,tp,kv re v. 3.0e, feb. 12, 2001 4194304-bi t ( 524288-word by 8-bi t) c mos s tat ic ram mi t subishi lsis 3 absolute maximum ratin gs pf 8 10 v i =gnd, v i =25mvrms, f =1mhz v o = gnd,v o =25mvrms, f =1mhz c i c o s ymbol parameter limits conditions units a ma a ma v icc 1 icc 2 icc 4 v ih v il i o icc 3 v oh1 i oh = -0.5ma v oh2 i oh = -0.05ma v ol i ol =2ma i i v i =0 ~ vcc s# =v ih or oe#=v ih, v i/o =0 ~ vcc vcc+0.3v 0.6 2.2 - 0.3 * 2.4 0.5 0.4 1 4530 20 vcc-0.5v 1 7 max t yp min dc electrical characteristics 70c 40c 2 f = 10mhz f = 1mhz - - - - - - - - suppl y v oltage input v oltage output v oltage power dissipation operating temperature storage temperature v mw c c conditions ta=25c 700 - 65 ~ +150 ratings v cc v i v o p d t a t stg - 0.5 * ~ +4.6 - 0.5 * ~ vcc + 0.5 0 ~ vcc s ymbol parameter units - 40 ~ +85 i- v ersion (industrial temp.) with respect to gnd f = 10mhz f = 1mhz 5 4530 75 85c -40 ~ +25c - 0.3 1 5 - - 40 - with respect to gnd with respect to gnd ( vcc=2.7 ~ 3.6v, unless otherwise noted) high-le v el input v oltage low-le v el input v oltage high-le vel output volta g e 1 high-le vel output volta g e 2 low-le v el output v oltage input leakage current output leakage current acti v e suppl y c urrent ( ac, cmos-le v el ) ( ac,ttl-le v el ) acti v e suppl y c urrent stand b y s uppl y current (cmos-le v el input) (ttl-le v el input) stand b y s uppl y current s# < 0.2v other inputs < 0.2v or > vcc-0.2v output-open s# =v il other inputs=v ih or v il output-open s# =v ih ,other inputs= 0 ~ vcc s# > vcc-0.2v other inputs=0~vcc * -3.0v in case o f ac (pulse width < 30ns) note 1: direction f or current f lowing into ic is indicated as positi v e (no mark). note 2: t y pical v alues are sampled at vcc=3.0v, and are not 100% tested. capacitance (vcc=2.7 ~ 3.6v, unless otherwise noted) s ymbol parameter conditions limits max t yp min units input capacitance output capacitance * -3.0v in case o f ac (pulse width < 30ns) vcc=3.6v, max. _ _ _ _ _ _ 0 ~ 70 standard (commercial temp.) 2 0 ~ +25c - 0.3 i- v ersion i- v ersion i- v ersion, standard
m5m5 v408bfp,tp,kv re v. 3.0e, feb. 12, 2001 4194304-bi t ( 524288-word by 8-bi t) c mos s tat ic ram mi t subishi lsis output disable time a ft er oe# high output enable time a f ter s# low output enable time a f ter oe# low output disable time a ft er s# high 4 t cr ns t a (s ) t a (oe) t dis (s ) t dis (oe) t en (s ) t en (oe) t v (a) t a (a) 25 25 1ttl cl dq 70 10 5 10 70 70 35 85 55 0 65 65 35 0 0 5 5 t cw t w (w) t su (a) t su (a-wh) t su (s ) t su (d) t h (d) t rec (w) t dis (w) t dis (oe) t en (w) t en (oe) 85 85 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns input rise time and f all time re f erence le v el output loads 2.7v~3.6v v ih =2.4v,v il =0.4v v oh =v ol =1.5v transition is measured 500mv f rom stead y state voltage.( f or t en ,t dis ) 5ns fig.1,cl=30pf cl=5pf (for ten,tdi s) ac electrical characteristics (vcc=2.7 ~ 3.6v, unle ss otherwi s e noted) (1) test conditions (2) read cycle s ymbol parameter limits units max min read c y cle time address access time chip select access time output enable access time data v alid time a fter address (3) w rite cycle s ymbol parameter limits units write c y cle time write pulse width address set up time address set up time with respect to w# high chip select set up time data set up time data hold time write reco v er y time output disable time a ft er w# low output disable time a ft er oe# high output enable time a f ter w# high output enable time a f ter oe# low suppl y v oltage input pulse fig.1 output load including scope and jig capacitance 45 25 25 max min 10 5 10 25 25 -70h, -70hi -85h, -85hi max min max min 25 25 5 5 70 55 0 65 65 35 0 0 -70h, -70hi -85h, -85hi
m5m5 v408bfp,tp,kv re v. 3.0e, feb. 12, 2001 4194304-bi t ( 524288-word by 8-bi t) c mos s tat ic ram mi t subishi lsis t en (w) 5 t a (a) t a (s) t v (a) t dis (s) t a (oe) t en (oe) t dis (oe) t cr t h (d) t su (d) dq 1~8 t su (s) t su (a-wh) t en (oe) t dis (oe) t w (w) t rec (w) t su (a) t dis (w) t cw t en (s) w# = "h" le v el a 0~18 dq 1~8 a 0~18 oe# oe# s# w# s# (4) timin g diagrams read cycle (note3) (note3) (note3) (note3) valid data write cycle ( w# control mode ) data in stable (note3) (note3) (note4) (note4) (note6)
m5m5 v408bfp,tp,kv re v. 3.0e, feb. 12, 2001 4194304-bi t ( 524288-word by 8-bi t) c mos s tat ic ram mi t subishi lsis 6 note 3: hatching indicates the state is "don't care". note 4: a write occurs during the o v erlap o f a low s# and a low w#. note 5: i f w# goes low simultaneousl y with or prior to s#,the output remains in the high impedance state. note 6: don't appl y in v erted phase signal externall y when dq pin is in output mode. t h (d) t su (d) dq 1~8 t su (s) t rec (w) t su (a) t cw a 0~18 w# s# write cycle (s# control mode) data in stable (note3) (note3) (note4) (note5) (note6) (note4)
m5m5 v408bfp,tp,kv re v. 3.0e, feb. 12, 2001 4194304-bi t ( 524288-word by 8-bi t) c mos s tat ic ram mi t subishi lsis 7 t su (pd) t rec (pd) ns 0 5 ms 2.0v t su (pd) 2.7v2.7v 2.0v t rec (pd) s# > vcc - 0.2v vcc v v 2.0 vcc (pd) v i (s) icc (pd) 2.0 s# a power do wn characteristics (1) electrical characteristics s ymbol parameter test conditions limits min t y p. max units power down suppl y v oltage chip select input s# power down s upply current vcc=3.0v , s# > vcc-0.2v, other inputs = 0 ~ vcc (2) timin g requirements s ymbol parameter test conditions limits min t yp max units power down set up time power down reco v er y t ime (3) timin g diagram s# control mode *t y pical v alues are sampled, and are not 100% tested. 0.4* 15 30 - - - - -40~ 25c 70 c 85 c 40 c 3 1 1* 0.4* 1 0~ 25c i-version i-version standard, i-version standard - - - _ _
m5m5 v408bfp,tp,kv re v. 3.0e, feb. 12, 2001 4194304-bi t ( 524288-word by 8-bi t) c mos s tat ic ram mi t subishi lsis 8 revision history revision no. k0.1e k0.2e k1.0e k2.0e 3.0e hi story the first edition added m5m5v408b fp/tp/rt the first product version 1) speed items revised: 70ns added and 100ns deleted 2) icc3 and icc(pd) limits revised 1) product lineup revised 2) symbol notations revised: s -> s#, w-> w#, o e -> oe# date mar. 5, 1998 jul.30, 1998 sep.7, 1998 mar.10,1999 f eb .12, 2002 remarks preliminary preliminary --- --- ---
keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibili ty for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mi tsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
|
